1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory having plural memory cells each provided with a floating gate and a control gate, and to a method of the same.
2. Description of the Related Art
A type of nonvolatile semiconductor memory, in which transistors (memory cells), each having a floating gate and a control gate, are arranged in a matrix, is known. Such a nonvolatile semiconductor memory is provided with plural source lines, each electrically connected with source regions of transistors belonging to the same row. It is also provided with plural bit lines each electrically connected with drain regions of transistors belonging to the same column. Further, it is provided with plural word lines each including the floating gate and the control gate of the transistors belonging to the same row.
Conventionally, a nonvolatile semiconductor memory like this is fabricated in accordance with the following procedure.
First, a pad oxide layer (pad SiO.sub.2 layer) and silicon nitride layer (Si.sub.3 N.sub.4 layer) are formed on the entire surface of a silicon substrate (Si wafer). Subsequently, a resist pattern, which covers only areas where source lines and transistors will be created, is formed on the silicon nitride layer using lithography. Then, several processes, starting with an etching process are performed, whereby silicon dioxide areas, i.e., field areas for accomplishing isolation between memory cells, are formed on areas where no source line and no memory cell are formed.
Once the structure which has field areas and an area where no silicon dioxide exists (hereinafter, called active area) on the surface is completed, the entire surface is again covered with several layers for word lines. Thereafter, a resist pattern for patterning the layers is formed through lithography. The layers are then etched using the resist pattern as a mask, whereby the word lines are formed. After forming the word lines, a doping process is carried out. Then, an intermediate insulating layer covering the entire surface is formed. Further, a resist pattern, which covers areas except the drain regions, is formed on the intermediate insulating layer using lithography. Then, the intermediate insulating layer is etched using the resist pattern as a mask, and holes reaching the drain regions (i.e. drain contact holes) are formed. Thereafter, a conducting material (A1) is deposited on the surface, and the deposited conducting material is patterned, whereby the bit lines are formed.
Note that, for details of a fabrication procedure for a nonvolatile semiconductor memory like this, reference may be made for instance, to Japanese Patent Application Laid-Open No. 64-77160, published in 1989.
As stated above, in the conventional nonvolatile semiconductor memory, both the word lines and the source lines are formed using resist patterns (lithography). Therefore, when a nonvolatile semiconductor memory to be fabricated with the above structure is designed, intervals between the word lines and the source lines are determined with consideration given to the accuracy of alignment of the photomask. That is, intervals between the word lines and the source lines are designed in such a manner that a nonvolatile semiconductor memory of normal function can be obtained when the resist pattern is formed at a position distant from the standard position. As a result, in the conventional nonvolatile semiconductor memory, there are useless areas having no effect on the function around source lines.
Further, the conventional nonvolatile semiconductor memory also uses lithography when drain contact holes are formed. At this time, when the drain contact holes are directly in contact with the floating gates or the control gates of the word lines, a nonvolatile semiconductor memory which does not function normally is fabricated. Consequently, the design relative to the drain contact holes is also made with consideration given to the accuracy of alignment of the photomask. As a result, useless areas, which have no effect on the memory function, also exist around drain contact holes in the conventional nonvolatile memory.